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MRF89XA
2.16.3
SYNC CONTROL REGISTER
DETAILS
REGISTER 2-19:
SYNCREG: SYNC CONTROL REGISTER (ADDRESS:0x12) (POR:0x18)
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
r
POLFILEN
BSYNCEN
SYNCREN
SYNCWSZ<1:0>
SYNCTEN<1:0>
—
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7
bit 6
bit 5
bit 4-3
bit 2-1
bit 0
POLFILEN: Polyphase Filter Enable bit
This bit enables the polyphase filter in OOK Receive mode.
1 = Polyphase filter enabled
0 = Polyphase filter disabled (default)
BSYNCEN: Bit Synchronizer Enable bit
This bit controls the enabling and disabling of the bit synchronizer in Continuous receive mode.
1 = Bit Synchronizer disabled
0 = Bit Synchronizer enabled (default)
SYNCREN: SYNC Word Recognition Enable bit
1 = ON
0 = OFF (default)
SYNCWSZ<1:0>: SYNC Word Size bit
11 = 32 bits (default)
10 = 24 bits
01 = 16 bits
00 = 8 bits
SYNCTEN<1:0>: SYNC Word Tolerated Error Numbers
These bits indicate the number of errors tolerated in the SYNC word recognition.
11 = 3 Errors
10 = 2 Errors
01 = 1 Errors
00 = 0 Errors (default)
Reserved: Reserved bit; do not use
0 = Reserved (default)
DS70622C-page 44
Preliminary
? 2010–2011 Microchip Technology Inc.
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